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ISL5416
Pin Descriptions
(Continued)
INTERNAL
NAME
FSYNCA
FSYNCB
FSYNCC
FSYNCD
OEA
OEB
OEC
OED
TYPE
O
O
O
O
I
I
I
I
PULL-UP/DOWN
PULL UP
PULL UP
PULL UP
PULL UP
DESCRIPTION
Frame Synchronization output signal for bus Aout(15:0).
Frame Synchronization output signal for bus Bout(15:0).
Frame Synchronization output signal for bus Cout(15:0).
Frame Synchronization output signal for bus Dout(15:0).
Output three-state enable for Parallel Data Output bus A. Active low.
Output three-state enable for Parallel Data Output bus B. Active low.
Output three-state enable for Parallel Data Output bus C. Active low.
Output three-state enable for Parallel Data Output bus D. Active low.
MICROPROCESSOR INTERFACE
P(15:0)
ADD(2:0)
WR
or
DSTRB
RD
or
RD/WR
I/O
I
I
I
Microprocessor Interface Data bus. See Microprocessor Interface Section . P15 is the MSB.
Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section .
Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode
Control ( μ P MODE) is low, data transfers (from P(15:0) to the internal write holding register) occur on
the low to high transition of WR when CE is asserted (low). When the μ P MODE control is high this
input functions as a data strobe DSTRB control. In this mode with RD/WR low, data t ransfers (from
P(15:0) to the internal write holding register) occur on the low to high transition of DSTRB. With
RD/WR high the data from the address specified is placed on P(15:0) when DSTRB is low. See the
Microprocessor Interface Section .
Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode
Control ( μ P MODE) is low, the data from the address specified is placed on P(15:0) when RD is
asserted (low) and CE is asserted (low). When the μ P MODE control is high this input functions as
a Read/Write control input. Data is read from P(15:0) when RD/WR high or written to the
appropriate register when low. See the Microprocessor Interface Section .
μ P MODE
I
PULL DOWN
Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the
Microprocessor Interface. When 0, RD and WR, when 1, DSTROBE and RD/WR. When μ P MODE
is 0, the microprocessor interface consists of separate RD and WR strobes; when μ P MODE is 1, the
interface consists of a RD/WR control and a single data strobe. See the Microprocessor Interface
Section .
CE
I
6
Microprocessor Interface Chip Select. Active low. This pin has the same timing requirements as the
address pins.
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